![]() The Xilinx 7 series “MultiBoot” featureīefore we can discuss the details of our variant 3, let’s revisit the Xilinx 7 series “MultiBoot” feature which we’re soon going to abuse for our own purpose. In the following sections, we present a third variant which combines the fast configuration time of variant 1 with the saved cost and simplicity of variant 2. The reason is that the microcontroller needs to sequentially read and send data blocks and the transfer speed is limited by the SPI bus speed of the microcontroller (33 MHz for the FX3) and its ability to quickly switch bit-bang GPIOs for the FPGA configuration interface. Unfortunately, the system startup time is now much slower (in our case about 5–10 seconds vs. This alternative variant saves the cost of the second flash chip and the corresponding board space and simplifies the firmware update process as only the microcontroller needs to write to the flash chip. ![]() ![]() Second, the microcontroller configures the FPGA in “Slave Serial” or “Slave SelectMAP” mode by reading blocks of the bitstream data and sending them to the FPGA. Variant 2: Single flash chip connected to the microcontroller, configuration of the FPGA in “Slave Serial” or “Slave SelectMAP” modeįirst, the microcontroller boots from the flash chip via its SPI bus. ![]()
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. Archives
December 2022
Categories |